cy8c20142 capsense lite - 4 configurable ios cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-32159 rev. ** revised september 19, 2007 features four configurable ios supporting ? capsense buttons ? led drive ? interrupt outputs ? wake on interrupt input ? user defined input/output 2.4v to 5.25v operating voltage industrial temperature range: ?40c to +85c i 2 c slave interface for configuration reduce bom cost ? internal oscillator - no external oscillators or crystal ? free development tool - no external tuning components low operating current ? active current: continuous sensor scan - 1ma ? active current: no sensor scan - 30ua ? sleep current: no scan, continuous sleep - 2.6ua available in 8-pin soic package overview the capsense lite controller allows the control of four configurable ios that are configurable as capacitive sensing buttons or as gpios for driving leds or interrupt signals based on various button conditions. the gpios also configurable for waking up the device from sleep based on an interrupt input. the user has the ability to configure buttons, outputs, and parameters, through specific commands sent to the i 2 c port. the ios have the flexibility to be mapped to capacitive buttons and/or as standard gpio functions such as interrupt output or input, led drive and digital mapping of input to output using simple logical operations. this enables easy pcb trace routing and reduces the pcb size and stack up. capsense lite products are designed for easy integration into complex products. architecture the logic block diagram shows the internal architecture of cy8c20140. the user can configure regist ers with parameters needed to adjust the operation and sens itivity of the capsense system. cy8c20140 supports a standard i2c serial communications interface that allows the host to configure the device and to read sensor information in real time through easy register access. the capsense lite core the capsense lite core has a powerful configuration and control block. it en compasses sram for data storage, an interrupt controller, sleep and watchdog timers. system resources provide additional capability, such as a configurable i 2 c slave communication interface and various system resets. the analog system is composed of the capsense psoc block and an internal 1.8v analog re ference, which together support capacitive sensing of up to 4 inputs. [+] feedback
cy8c20142 document number: 001-32159 rev. ** page 2 of 10 logic block diagram 4 configurable ios capsense lite core 2kb flash 512b sram [+] feedback
cy8c20142 document number: 001-32159 rev. ** page 3 of 10 pinouts figure 1. pin diagram - 8 soic i2c scl vdd gp0[1] gp0[0] gp1[1] i2c sda gp1[0] vss table 1. pin definitions - 8 soic pin no name description 1 vss ground connection 2i 2 c scl i 2 c clock 3i 2 c sda i 2 c data 4 gp1[0] configurable as capsense or gpio 5 gp1[1] configurable as capsense or gpio 6 gp0[0] configurable as capsense or gpio 7 gp0[1] configurable as capsense or gpio 8 vdd supply voltage [+] feedback
cy8c20142 document number: 001-32159 rev. ** page 4 of 10 the capsense analog system the analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware performs capacitive sensing and scanning without requiring external components. capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins is completed quickly and easily across multiple pins. additional system resources system resources provide addi tional capability useful to complete systems. additional resources are low voltage detection and power on reset. the i 2 c slave provides 50, 100, or 400 khz communication over two wires. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels and the advanced por (power on reset) circuit eliminates t he need for a syst em supervisor. an internal 1.8v reference provides an absolute reference for capacitive sensing. i 2 c interface the two modes of operation for the i 2 c interface are: device register configuration and status read/write for controller command execution the i 2 c address is programmable du ring configuration. it can be locked to prevent accidental change by setting a flag in a configuration register. electrical specifications absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25c 25c. extended duration storage tempera- tures above 65c degrade reliability. t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any gpio pin ?25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c [+] feedback
cy8c20142 document number: 001-32159 rev. ** page 5 of 10 dc electrical characteristics dc chip level specifications parameter description min typ max unit notes v dd supply voltage 2.40 ? 5.25 v i dd supply current ? 1.5 2.5 ma conditions are v dd = 3.0v, t a = 25c i sb27 sleep mode current with por and lvd active. mid temperature range ?2.6 4 av dd = 2.55v, 0c < t a < 40c i sb sleep mode current with por and lvd active. ?2.6 5 av dd = 3.3v, ?40c < t a < 85c 5v and 3.3v dc general purpose io specifications parameter description min typ max unit notes r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 0 pins v dd ? 0.2 ? ? v ioh < 10 a, vdd > 3.0v, maximum of 10 ma source current in all ios. v oh2 high output voltage port 0 pins v dd ? 0.9 ? ? v ioh = 1 ma, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh3 high output voltage port 1 pins v dd ? 0.2 ? ? v ioh < 10 a, vdd> 3.0v, maximum of 10 ma source current in all ios. v oh4 high output voltage port 1 pins v dd ? 0.9 ? ? v ioh = 5 ma, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh4 high output voltage port 1 pins v dd ? 0.9 ? ? v ioh = 5 ma, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh5 high output voltage port 1 pins with ldo regulator enabled 2.75 3.0 3.2 v ioh < 10 a, vdd> 3.1v, maximum of 4 ios all sourcing 5ma. v oh6 high output voltage port 1 pins with ldo regulator enabled 2.2 ? ? v ioh = 5 ma, vdd > 3.1v, maximum of 20 ma source current in all ios. v oh7 high output voltage port 1 pins with ldo regulator enabled 2.1 2.4 2.5 v ioh < 10 a, vdd > 3.0v v oh8 high output voltage port 1 pins with ldo regulator enabled 2 ? ? v ioh < 200 a, vdd > 3.0v v ol low output voltage ? ? 0.75 v iol = 20 ma, vdd > 3v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[3]). v il input low voltage ? ? 0.8 v vdd = 3.0 to 5.25v. v ih input high voltage 2.0 ? ? v vdd = 3.0 to 5.25v. v h input hysteresis voltage - 140 - mv i il input leakage ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent. te m p = 2 5 c . c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. te m p = 2 5 c . [+] feedback
cy8c20142 document number: 001-32159 rev. ** page 6 of 10 2.7v dc general pur pose io specifications parameter description min typ max unit notes r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 0 pins v dd ? 0.2 ? ? v ioh < 10 a, maximum of 10 ma source current in all ios. v oh2 high output voltage port 0 pins v dd ? 0.5 ? ? v ioh = 0.2 ma, maximum of 10 ma source current in all ios. v oh3 high output voltage port 1 pins v dd ? 0.2 ? ? v ioh < 10 a, maximum of 10 ma source current in all ios. v oh4 high output voltage port 1 pins v dd ? 0.5 ? ? v ioh = 2 ma, maximum of 10 ma source current in all ios. v ol low output voltage ? ? 0.75 v iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[3]). v olp1 low output voltage port 1 pins ? ? 0. 4 v iol=5ma maximum of 50ma sink current on even port pins (for example, p0[2] and p1[4]) and 50ma sink current on odd port pins (for example, p0[1] and p1[3]). 2.4<=vdd<=3.6 v il input low voltage ? ? 0.8 v vdd = 2.4 to 3.0v. v ih input high voltage 2.0 ? ? v vdd = 2.4 to 3.0v. v h input hysteresis voltage - 60 - mv i il input leakage ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent. temp = 25c. c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. temp = 25c. 3.0v gpio specifications parameter description min typ max unit notes v ih input high voltage 1.6 ? ? v 3.0v<=vdd<=3.6v v oh1 h i g h o u t p u t vo l t a g e port 1 pins with 1.8v ldo regulator enabled 1 . 6 1 . 8 1 . 9 5 v i o h < 1 0 u a 3 . 0 v < = v d d < = 3 . 6 v 0c<=ta<=85c v oh2 h i g h o u t p u t vo l t a g e port 1 pins with 1.8v ldo regulator enabled 1 . 5 ? ? v i o h < 1 0 0 u a 3 . 0 v < = v d d < = 3 . 6 v 0c<=ta<=85c [+] feedback
cy8c20142 document number: 001-32159 rev. ** page 7 of 10 dc por and lvd specifications parameter description min typ max unit notes v ppor0 v ppor1 v ppor2 v dd value ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.36 2.60 2.82 2.40 2.65 2.95 v v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. vlvd0 vlvd1 vlvd2 vlvd3 vlvd4 vlvd5 vlvd6 vlvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.39 2.54 2.75 2.85 2.96 ? ? 4.52 2.45 2.71 2.92 3.02 3.13 ? ? 4.73 2.51 2.78 2.99 3.09 3.20 ? ? 4.83 v v v v v v v v [+] feedback
cy8c20142 document number: 001-32159 rev. ** page 8 of 10 ac electrical characteristics ac general purpose io specifications parameter description 5.0v/3.3v 2.7v unit notes min max min max trise0 rise time, strong mode, cload = 50pf, port 0 15 80 15 100 ns vdd = 2.4v to 3.0v, 10% - 90% trise1 rise time, strong mode, cload = 50pf, port 1 10 50 10 70 ns vdd = 2.4v to 3.0v, 10% - 90% tfall fall time, strong mode, cload = 50pf, all ports 10 50 10 70 ns vdd = 2.4v to 3.0v, 10% - 90% ac i 2 c specifications parameter description standard mode fast mode unit notes min max min max f scli2c scl clock frequency 0 100 0 400 khz fast mode not supported for vdd < 3.0v t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 - 0.6 - s t lowi2c low period of the scl clock 4.7 - 1.3 - s t highi2c high period of the scl clock 4.0 - 0.6 - s t sustai2c setup time for a repeated start condition 4.7 - 0.6 - s t hddati2c data hold time 0 - 0 - s t sudati2c data setup time 250 - 100 - ns t sustoi2c setup time for stop condition 4.0 - 0.6 - s t bufi2c bus free time between a stop and start condition 4.7 - 1.3 - s t spi2c pulse width of spikes suppressed by the input filter --050ns figure 2. definition for timing for fast/standard mode on the i 2 c bus sda scl s sr s p t bufi2c t spi 2c t hdstai2c t sustoi 2c t sustai 2c t lowi2c t highi2c t hddati2c t hdstai 2c t sudati 2c [+] feedback
cy8c20142 document number: 001-32159 rev. ** page 9 of 10 ordering information ordering code package diagram package type operating temperature CY8C20140-SX1I 51-85066 8 soic industrial thermal impedances by package package typical ja [1] 8 soic 127.22 c/w note 1. t j = t a + power x ja solder reflow peak temperature package minimum peak temperature [2] maximum peak temperature 8 soic 240 c 260 c note 2. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5c with sn- pb or 245 5c with sn-ag-cu paste. refer to the solder manufacturer specifications. package diagram figure 3. 8 - pin (150-mil) soic seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-*c [+] feedback
document number: 001-32159 rev. ** revised september 19, 2007 page 10 of 10 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c20142 ? cypress semiconductor corporation, 2007. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy8c20142 capsense lite - 4 configurable ios document number: 001-32159 rev. ecn. issue date orig. of change description of change ** 1494145 see ecn tup/aesa new datasheet [+] feedback
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